Semiconductor device and method of fabricating the same

ABSTRACT

An adhesion layer made from Al film or Ti film is formed on Cu electrode pad portions as external connection terminals of a Cu interconnection layer of an LSI formed on the surface layer of a semiconductor substrate. A BLM film having a stacked structure of Cr/Cu/Au or Ti/Cu/Au is formed on the adhesion layer. Solder ball bumps made from Pb and Sn are formed on the BLM film. The adhesion layer ensures a high adhesion strength and a high electric contact characteristic between the Cu electrode pad portions and the BLM film, that is, between the Cu electrode pads and the solder ball bumps.

RELATED APPLICATION DATA

The present application is a reissue application of application Ser. No.09/313,172, now U.S. Pat. No. 6,545,355, issued Apr. 8, 2003, whichclaims priority to Japanese Application No. P10-141481 filed May 22,1998, which application is incorporated herein by reference to theextent permitted by law.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and a method offabricating the semiconductor device, and particularly to asemiconductor device in which solder bumps are formed on electrode padsvia a barrier metal film is and a method of fabricating thesemiconductor device.

To increasingly progress miniaturization of electronic equipment, it isimportant how improve the mounting density of electronic parts. Withrespect to semiconductor ICs (Integrated Circuits), studies have beenactively made to develop such a high density mounting technology as todirectly mount a bare chip on a printed wiring board, typically aflip-chip mounting method in place of the conventional packaging method.

The flip-chip mounting method is represented by an Au (gold) stud bumpmethod or a solder ball bump method, and further, it includes variousother methods covering a wide range from those at the prototype stage tothose at the commercially practical stage. The present applicant hasdeveloped in advance of time a mass-production technology for formingsolder ball bumps on a wafer level including a number of chips byapplying the LSI (Large-Scale Integrated Circuit) fabrication process,and has filed a number of the associated patent applications andsimultaneously put consumer-oriented equipment produced on the basis ofsuch a technology, for example, a micro digital camcorder, to thus earlycommercialize the next-generation LSI mounting technology.

In formation of solder ball bumps, a barrier metal film is providedbetween Al (aluminum) based electrode pads of an LSI and the bumps inorder to improve the adhesion between the electrode pads and the bumpsand prevent the mutual diffusion therebetween. In particular, for thesolder ball bump method, since the barrier metal film exerts a largeeffect on the finished shapes of bumps, such a film is generally calleda BLM (Ball Limiting Metal) film.

In general, the BLM film used for solder bumps has a three-layerstructure of Cr (chromium) film/Cu (copper) film/Au film. In thisthree-layer structure, the bottom Cr film functions as an adhesion layerfor ensuring good adhesion with Al electrode pads; the intermediate Cufilm functions as a barrier layer for preventing the diffusion of solderfrom solder bumps; and the top Au film functions as an oxidationpreventive film for preventing the oxidation of the Cu film.

A related art method of forming solder bumps using such a BLM film willbe described below with reference to FIGS. 8 to 12.

First, an Al based electrode pad 32 made from Al or an Al—Cu alloy isformed on a connection of a flip-chip IC (not shown) formed on thesurface of a semiconductor substrate 30. The entire surface of thesubstrate is covered with a passivation film (surface protective film)34 made from polyimide film or silicon nitride film, and a BLM film 36is formed in such a manner as to be connected to the Al based electrodepad 32 via a connection hole opened in the passivation film 34 (see FIG.8).

The entire surface of the substrate is coated with a sufficiently thickphotoresist film 38, and the photoresist film 38 is patterned byphotolithography to form an opening 40 having a diameter being largeenough to expose the BLM film 36 and a portion of the passivation film34 around the BLM film 36 (see FIG. 9).

A solder vapor-deposition film 42 made from Pb (lead) and Sn (tin) isformed over the entire surface of the substrate by use of, for example avapor-deposition method. At this time, since the end, positioned at theedge of the opening 40, of the photoresist film 38 is largely stepped,the solder vapor-deposition film 42 is divided into a soldervapor-deposition film 42a located on both the BLM film 36 and theportion of the passivation film 34 around the BLM film 34 in the opening40 and a solder vapor-deposition film 42b located on the photoresistfilm 38 (see FIG. 10).

The solder vapor-deposition film 42b located on the photoresist film 38is removed together with the photoresist film 38 by a lift-off method.The lift-off method is performed by dipping the wafer in a resistseparation solution and heating/oscillating the wafer in the solution,to lift-off the photoresist film 38. In this way, only the soldervapor-deposition film 42a, which covers the BLM film 36 and the portionof the passivation film 34 around the BLM film 36, remains (see FIG.11).

The solder vapor-deposition film 42a is then subjected to wet-backtreatment. That is to say, the solder vapor-deposition film 42a iscoated with flux and is fused by heat-treatment, to finally form asolder ball bump 44 connected to the BLM film 36. In this way, asemiconductor device is fabricated, in which the solder ball bumps 44are formed via the BLM film 36 on the Al based electrode pads 32 formedon the connections of the flip-chip IC formed on the surface of thesemiconductor substrate 30 (see FIG. 12).

While Al has been used as an interconnection material of LSIs for a longtime, the use of Al has come to cause serious problems associated withdelay of signals or deterioration in the reliability in multipleinterconnection layers along with tendency toward higher integration,finer-geometries, and higher operational speed of LSIs.

In place of such a conventional material Al, Cu (copper) is expected asan interconnection material of the next-generation LSIs and is nearingpractical use. Cu has a resistivity lower about 40% than that of Al (theresistivity of Al is about 2.8 μΩcm while the resistivity of Cu is about1.7 μΩcm), and further Cu has a high resistance againstelectromigration. Accordingly, the use of Cu is expected to furtherreduce the resistance of the LSIs and improve the reliability thereof.

However, since the above-described process of forming solder ball bumpson electrode pads via a BLM film is predicated on the use of Al basedelectrode pads, if such a process is applied to an LSI using Cuelectrode pads as terminals of Cu interconnections in place of theconventional Al based electrode pads as terminals of Al basedinterconnections, there may occur the following problem. Namely, sincethe adhesion strength between the BLM film and the Cu electrode pads islowered, there may easily arise the falling of solder ball bumps from asemiconductor chip upon mounting of the semiconductor chip on a printedwiring board or the failure in electric contact characteristic betweenthe Cu electrode pads and the solder ball bumps when the semiconductorchip undergoes a temperature cycle or a high temperature load, therebyexerting adverse effect on the device reliability.

Consequently, it is desired to establish a fabrication process of stablyforming solder ball bumps with a high-reliability to the next-generationLSIs adopting a Cu interconnection material.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor devicewith a high-reliability and a high-durability, which is capable offorming solder bumps on electrode pads made from a metal other than Alwithout degrading the adhesion strength between the electrode pads andthe solder bumps and the electric contact characteristic therebetween,and to provide a method of fabricating the semiconductor device.

To achieve the above object, according to a first aspect of the presentinvention, there is provided a semiconductor device including: electrodepads provided on a base; and solder bumps formed on the electrode padsvia a barrier metal film; wherein an adhesion layer is formed betweenthe electrode pads and the barrier metal film for increasing theadhesion therebetween.

The electrode pads is preferably made from Cu or an alloy containing Cu(hereinafter, these pads are referred to as “Cu based electrode pads”).

The adhesion layer is preferably made from at least one kind of metalselected from a group consisting of Al, Ti (titanium), Cr, Co (cobalt),Ni (nickel), Mo (molybdenum), Ag (silver), Ta (tantalum), W (tungsten)and Au, or an alloy containing the at least one kind of metal.

In the semiconductor device according to the first aspect of the presentinvention, since the adhesion layer is formed between the electrode padsand the barrier metal for increasing the adhesion therebetween, even ifthe electrode pads are changed from the convention Al based electrodepads into the Cu based electrode pads, it is possible to preventdegradation of the adhesion strength between the Cu based electrode padsand the solder bumps and the failure of the electric contactcharacteristic therebetween. That is to say, in order to keep up withthe next-generation high speed LSIs adopting Cu based interconnections,the function of the barrier metal film having been used for improvingthe adhesion between electrode pads and solder bumps is reinforced byprovision of the adhesion layer.

Accordingly, the solder ball bumps appropriate to the next-generationhigh speed LSI adopting the Cu interconnection layer can be formed, andsince the barrier metal function is reinforced by adding the adhesionlayer to the conventional barrier metal film, even if variousheat-treatments are applied to the substrate after formation of thesolder layer, it is possible to effectively prevent thermal diffusion ofsolder, and hence to obtain good electric contact characteristic betweenthe finally formed solder bumps and the Cu based electrode pads and alsoincrease the adhesion strength therebetween. This makes it possible toimprove the reliability and durability of a device product on which thesemiconductor chip is mounted by the flip-chip mounting method. Insummary, according to the semiconductor device of the first aspect ofthe present invention, it is possible to improve the electric contactcharacteristic, reliability, and durability of a device product on whichthe next-generation high speed LSI chip adopting Cu interconnections ismounted by the flip-chip mounting method.

According to a second aspect of the present invention, there is provideda method of fabricating a semiconductor device in which solder bumps areformed on electrode pads provided on a base via a barrier metal film,the method including: a first step of forming a passivation film in sucha manner as to cover electrode pads; forming a resist film on thepassivation film and patterning the resist film into a specific shape;and selectively etching the passivation film using the resist film as amask to expose the electrode pads; a second step of forming an adhesionfilm over the entire surface of the base; and removing a first portion,located on the resist film, of the adhesion film together with theresist film by a lift-off method, to allow only a second portion,located on the electrode pads, of the adhesion layer to remain; and athird step of forming solder bumps on the second portion of the adhesionlayer located on the electrode pads via a barrier metal film.

The second step preferably includes a step of forming the adhesion layerover the entire surface of the base by a sputtering method, anelectrolytic plating method, or a CVD (Chemical Vapor Deposition)method.

In the method of fabricating a semiconductor device according to thesecond aspect of the present invention, the passivation film isselectively etched using the resist film patterned into a specific shapeas a mask to expose the electrode pads, and of the adhesion layer formedover the entire surface of the base, the unnecessary portion of theadhesion layer located on the resist film is removed together with theresist film by lifting-off the resist film, to allow only the portion ofthe adhesion layer located on the electrode pads to remain. That is tosay, the resist film patterned into a specific shape is used for boththe etching mask and the lift-off film. Accordingly, it is possible toeliminate the necessity for provision of the step of forming a resistfilm for forming the adhesion layer only on the electrode pads and thelithography step for patterning the resist film, and hence toeffectively form the adhesion layer in self-alignment over the entiresurfaces of the electrode pads exposed by selective etching of thepassivation film without increasing the number of processing steps.

Accordingly, even if the electrode pads are changed from the Al basedelectrode pads into the Cu based electrode pads, the adhesion layer canbe effectively formed in self-alignment on the entire surfaces of the Cubased electrode pads. This makes it possible to increase the adhesionbetween the Cu based electrode pads and the barrier metal film and henceto prevent the degradation of adhesion strength between the Cu basedelectrode pads and the solder bumps and the failure in electric contactcharacteristic therebetween. In summary, according to the method offabricating the semiconductor device of the second aspect of the presentinvention, it is possible to improve the electric contactcharacteristic, reliability, and durability of a device product on whichthe next-generation high speed LSI chip adopting Cu interconnections ismounted by the flip-chip mounting method.

While description has been made of the case adopting a Cu based materialas the interconnection material of the next-generation high speed LSI,the present invention is not limited thereto. Even if a metal other thanCu is adopted as the interconnection material, the present invention cankeep up with the future LSIs by selecting the material of the adhesionlayer for increasing the adhesion between electrode pads and a barriermetal film in consideration of the new interconnection material otherthan Cu.

In this way, the semiconductor device and the fabrication method thereofaccording to the present invention is very useful to realize asemiconductor device designed on the basis of the fine design rule andrequired having high-integration, high-performance, andhigh-reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view showing a semiconductor device according toone embodiment of the present invention, in which a BLM film is formedon a Cu electrode pad portion of an LSI via an adhesion layer and asolder ball bump is formed on the BLM film;

FIG. 2 is a sectional view illustrating a first step of a method offabricating the semiconductor device shown in FIG. 1, in which a resistfilm having a pad opening is formed on a silicon nitride film as apassivation film;

FIG. 3 is a sectional view illustrating a second step of the method offabricating the semiconductor device shown in FIG. 1, in which thesurface of the Cu electrode pad is exposed by selective dry etching ofthe silicon nitride film;

FIG. 4 is a sectional view illustrating a third step of the method offabricating the semiconductor device shown in FIG. 1, in which theadhesion layer is divided into a portion on the Cu electrode pad portionin the pad opening and a portion formed on the resist film;

FIG. 5 is a sectional view illustrating a fourth step of the method offabricating the semiconductor device shown in FIG. 1, in which theunnecessary portion of the adhesion layer located on the resist film isremoved together with the resist film by lifting-off the resist film, toallow only the portion of the adhesion layer located on the Cu electrodepad in the pad opening to remain;

FIG. 6 is a sectional view illustrating a fifth step of the method offabricating the semiconductor device shown in FIG. 1, in which a BLMfilm is formed in such a manner as to be connected to the adhesion layervia an opening formed in a polyimide film as a passivation film;

FIG. 7 is a sectional view illustrating a sixth step of the method offabricating the semiconductor device shown in FIG. 1, in which a solderball bump is formed on the BLM film;

FIG. 8 is a sectional view illustrating a first step of a related artmethod of forming solder bumps, in which a BLM film is formed in such amanner as to be connected to an Al based electrode pad via a connectionhole opened in a passivation film formed on a semiconductor substrate;

FIG. 9 is a sectional view illustrating a second step of the related artmethod of forming solder bumps, in which an opening for exposing the Albased electrode pad and a portion of the passivation film around the Albased electrode pad is formed in a sufficiently thick photoresist film;

FIG. 10 is a sectional view illustrating a third step of the related artmethod of forming solder bumps, in which a solder vapor-deposition filmis formed in such a manner as to be divided into one on the BLM film andthe portion of the passivation film around the BLM film in the openingand the other on the photoresist film;

FIG. 11 is a sectional view illustrating a fourth step of the relatedart method of forming solder bumps, in which a portion of the soldervapor-deposition film covering the bottom surface in the openingincluding the BLM film is allowed to remain by a lift-off method; and

FIG. 12 is a sectional view illustrating a fifth step of the related artmethod of forming solder bumps, in which a solder ball bump is formed onthe Al based electrode pad via the BLM film by heating and fusing thesolder vapor-deposition film using a wet-back method.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be described withreference to the accompanying drawings.

FIG. 1 is a sectional view showing a semiconductor device according toone embodiment of the present invention, and FIGS. 2 to 7 are sectionalviews illustrating sequential steps of a method of fabricating thesemiconductor device shown in FIG. 1.

As shown in FIG. 1, a LSI (not shown) formed in a surface layer of asemiconductor substrate 10 is subjected to multilayer interconnection bya Cu interconnection layer 12, and the entire surface of the substrate10 is covered with a silicon nitride film 14 as a passivation film.

A portion, over a Cu electrode pad portion 12a as an external connectionterminal of the Cu interconnection layer 12, of the silicon nitride film14 is selectively removed, and an adhesion layer 20a made from Al filmor Ti film is formed on the Cu electrode pad portion 12a.

The adhesion layer 20a and the silicon nitride film 14 are furthercovered with a polyimide film 22 as a passivation film. A portion, overthe adhesion layer 20a, of the polyimide film 22 is selectively removed,and a BLM film 24 having a stacked structure of Cr/Cu/Au or Ti/Cu/Au isformed on the adhesion layer 20a.

A solder ball bump 26 made from Pb and Sn is formed on the BLM film 24.

The method of fabricating the semiconductor device shown in FIG. 1 willbe described with reference to FIGS. 2 to 7.

First, an LSI (not shown) is formed in a surface layer of thesemiconductor substrate 10, and is subjected to multilayerinterconnection using a Cu interconnection layer 12. A silicon nitridefilm 14 as a passivation film is formed on the entire surface of thesubstrate 10.

The silicon nitride film 14 is coated with a resist film 16, and theresist film 16 is patterned into a specific shape by photolithography,to form a pad opening 18 in the resist film 16 at a position over a Cuelectrode pad portion 12a as an external connection terminal of the Cuinterconnection layer 12 (see FIG. 2).

The semiconductor substrate 10 is set in a magnetron RIE (Reactive IonEtching) apparatus. The silicon nitride film 14 is selectively removedby dry etching using the resist film 16 having the pad opening 18 as amask, to expose the surface of the Cu electrode pad portion 12a in thepad opening portion 18 (see FIG. 3).

The semiconductor substrate 10 is set in a sputter apparatus. The entiresurface of the substrate 10 is subjected to pre-treatment for filmformation by RF (Radio Frequency) plasma, and an adhesion layer 20 madefrom Al film or Ti film is formed by sputtering on the entire surface ofthe substrate 10. Of the adhesion layer 20, an adhesion layer 20a isformed on the Cu electrode pad portion 12a exposed in the pad opening18, and an unnecessary adhesion layer 20b is formed on the resist film16. To be more specific, the adhesion layers 20a and 20b are separatedfrom each other by the stepped portion having a thickness equivalent tothe total thickness of the resist film 16 and the silicon nitride film14 at the edge of the pad opening 18 (see FIG. 4).

The semiconductor substrate 10 is dipped in a resist separationsolution, followed by heating and oscillation, to remove the resist film16. At this time, the unnecessary adhesion layer 20b on the resist film16 is removed together with the resist film 16 by lifting-off the resistfilm 16. In this way, only the adhesion layer 20a remains on the Cuelectrode pad portion 12a in the pad opening portion 18 (see FIG. 5).

A polyimide film 22 as a passivation film is formed on the entiresurface of the substrate. A portion, over the adhesion layer 20a, of thepolyimide film 22 is selectively removed by etching, to form an openingfrom which the adhesion layer 20a is exposed.

Then, a BLM film 24 is formed in such a manner as to be connected to theadhesion layer 20a via the opening in accordance with the same manner asthat in the related art fabrication method, for example, using thelift-off method and sputtering method (see FIG. 6). The lift-off methodand sputtering method may be replaced with the sputtering method andetching method.

A high melting point vapor-deposition film (Pb:Sn=97:3) is formed insuch a manner as to cover only the BLM film 24 and a portion of thepolyimide film 22 around the BLM film 24 in accordance with the samemanner as that in the related art fabrication method shown in FIGS. 8 to12 using the lift-off method and vacuum vapor-deposition method. Thehigh melting point vapor-deposition film is then subjected to wet-back.To be more specific, the high melting point vapor-deposition film iscoated with flux and is fused by heating, to form a solder bump 26 madefrom Pb and Sn connected to the BLM film 24. The lift-off method andvacuum vapor-deposition method may be replaced with an electrolyticplating method or printing method.

In this way, a semiconductor device shown in FIG. 7 is obtained, inwhich the BLM film 24 is formed via the adhesion layer 20a on the Cuelectrode pad portion 12a as an external connection terminal of the Cuinterconnection layer 12 of the LSI (not shown) formed in the surfacelayer of the semiconductor substrate 10, and the solder ball bump 26 isformed on the BLM film 24.

Hereinafter, the etching condition for the silicon nitride film 14, theformation condition for the adhesion layers 20a and 20b, and theformation condition for the BLM film 24 in the above-describedembodiment of the present invention will be described with reference tothe following examples.

EXAMPLE 1

The selective etching of the silicon nitride film 14 with the resistfilm 16 taken as a mask was performed using the magnetron RIE apparatusunder the following condition:

-   -   flow rate of reactive gas: C₄F₈/CO=10/90 sccm    -   pressure: 2.0 Pa    -   RF power: 2.2 W/cm²    -   strength of magnetic field: 150 Gauss

The formation of an Al film as the adhesive layers 20a and 20b wasperformed using a normal sputter apparatus under the followingcondition:

-   -   DC power: 4.0 kW    -   flow rate of atmospheric gas: Ar=100 sccm    -   pressure: 0.5 Pa    -   temperature of wafer stage: room temperature    -   thickness of Al adhesion layer: 0.1 μm

The formation of each of films constituting the BLM film 24 having thestacked structure of Cr/Cu/Au was performed by a normal sputterapparatus under the following condition:

(1) Formation Condition of Cr Film

-   -   DC power: 3.0 kW    -   flow rate of atmospheric gas: Ar=75 sccm    -   pressure: 1.0 Pa    -   temperature of wafer stage: 50° C.    -   thickness of Cr film: 0.1 μm

(2) Formation Condition of Cu Film

-   -   DC power: 9.0 kW    -   flow rate of atmospheric gas: Ar=100 sccm    -   pressure: 1.0 Pa    -   temperature of wafer stage: 50° C.    -   thickness of Cu film: 1.0 μm

(3) Formation Condition of Au Film

-   -   DC power: 3.0 kW    -   flow rate of atmospheric gas: Ar=75 sccm    -   pressure: 1.5 Pa    -   temperature of wafer stage: 50° C.    -   thickness of Au film: 0.1 μm

EXAMPLE 2

The selective etching for the silicon nitride film 14 with the resistfilm 16 taken as a mask using the magnetron RIE apparatus under thefollowing condition:

-   -   flow rate of reactive gas: C₄F₈/CO=10/90 sccm    -   pressure: 2.0 Pa    -   RF power: 2.2 W/cm²    -   strength of magnetic field: 150 Gauss

The formation of a Ti film as the adhesive layers 20a and 20b wasperformed using a normal sputter apparatus under the followingcondition:

-   -   DC power: 5.0 kW    -   flow rate of atmospheric gas: Ar=100 sccm    -   pressure: 0.5 Pa    -   temperature of wafer stage: room temperature    -   thickness of Ti adhesion layer: 0.1 μm

The formation of each of films constituting the BLM film 24 having thestacked structure of Ti/Cu/Au was performed using a normal sputterapparatus under the following condition:

(1) Formation Condition of Ti Film

-   -   DC power: 4.0 kW    -   flow rate of atmospheric gas: Ar=75 seem    -   pressure: 1.0 Pa    -   temperature of wafer stage: 50° C.    -   thickness of Ti film: 0.05 μm

(2) Formation Condition of Cu Film

-   -   DC power: 9.0 kW    -   flow rate of atmospheric gas: Ar=100 sccm    -   pressure: 1.0 Pa    -   temperature of wafer stage: 50° C.    -   thickness of Cu film: 1.0 μm

(3) Formation Condition of Au Film

-   -   DC power: 3.0 kW    -   flow rate of atmospheric gas: Ar=75 sccm    -   pressure: 1.5 Pa    -   temperature of wafer stage: 50° C.    -   thickness of Au film: 0.1 μm

As described above, according to this embodiment, since the adhesionlayer 20a made from Al film or Ti film is formed between the Cuelectrode pad portion 12a as an external connection terminal of the Cuinterconnection layer 12 and the BLM film 24 having the stackedstructure of Cr/Cu/Au or Ti/Cu/Au, it becomes possible to enhanceadhesion between the Cu electrode pad portion 12a and the BLM film 24.As a result, even if the material of an interconnection layer of an LSIis changed from Al (conventional material) to Cu, it becomes possible toprevent the adhesion strength between the Cu electrode pad portion 12aand the BLM film 24 from being reduced due to the change of thematerial. This prevents the device reliability from being degraded dueto the falling of the solder ball bump 26 from the semiconductor chipupon mounting of the semiconductor chip on a printed wiring board or thefailure in electric contact characteristic between the Cu electrode padportion 12a and the solder ball bump 26 when the semiconductor chipundergoes a temperature cycle or a high temperature load.

Accordingly, the solder ball bump 26 appropriate to the next-generationhigh speed LSI adopting the Cu interconnection layer 12 can be formed,and since the barrier metal function is reinforced by adding theadhesion layer 20a to the BLM film 24, even if the semiconductor chipundergoes a thermal cycle test or a high temperature shelf test under asevere condition, it is possible to suppress the degradation of theadhesion strength and the electric contact characteristic between the Cuelectrode pad portion 12a and the solder ball bump 26, and hence tosignificantly improve the reliability and durability of the final deviceproduct on which the semiconductor chip is mounted by the flip-chipmounting method.

In this embodiment, the silicon nitride film 14 is selectively etchedusing the resist film 16 having the pad opening portion 18 as a mask toexpose the surface of the Cu electrode pad 12a, and of the adhesionlayers 20a and 20b formed of the Al film or Ti film over the entiresurface of the substrate, the adhesion layer 20b on the resist film 16is removed together with the resist film 16 by lifting-off the resistfilm 16, to allow only the adhesion layer 20a on the Cu electrode padportion 12a to remain. That is to say, the resist film 16 is used forboth the etching mask and the lift-off film. Accordingly, it becomespossible to eliminate the necessity for provision of the step of forminga resist film for forming the adhesion layer 20a only on the Cuelectrode pad portion 12a and the lithography step for patterning theresist film, and hence to effectively form the adhesion layer 20a inself-alignment over the entire surface of the Cu electrode pad portion12a exposed by selective etching of the silicon nitride film 14 withoutincreasing the number of the processing steps.

In this way, in combination with the function of the conventional BLMfilm 24 having been used to improve the adhesion between the Cuelectrode pad portion 12a and the solder ball bump 26 and prevent themutual diffusion therebetween, the adhesion layer 20a formed between theCu electrode pad portion 12a and the BLM film 24 exhibits an effect ofimproving the electric contact characteristic, reliability, anddurability of a device product on which the next-generation high speedLSI chip adopting the Cu interconnection layer 12 is mounted by theflip-chip mounting method.

In the above embodiment, description has been made using the twoexamples: one being configured by the combination of the Cu electrodepad portion 12a, the adhesion layer 20a formed of the Al film, and theBLM film 24 having the stacked structure of Cr/Cu/Au (Example 1); andthe other being configured as the combination of the Cu electrode padportion 12a, the adhesion layer 20a formed of the Ti film, and the BLMfilm 24 having the stacked structure of Ti/Cu/Au; however, the presentinvention is not limited thereto. For example, as the adhesion layer20a, there may be used a metal film other than the Al film or Ti film,for example, a Cr film, Co film, Ni film, Mo film, Ag film, Ta film, Wfilm or Au film. That is to say, a metal film capable of exhibiting goodadhesion between the Cu electrode pad portion 12a and the BLM film 24may be used as the adhesion layer 20a.

In the above embodiment, description has been made by way of the caseusing the Cu electrode pad portion 12a, that is, the Cu interconnectionlayer 12; however, the interconnection material of an LSI is not limitedto Cu but may be an alloy containing Cu. That is to say, the presentinvention can be applied to the case using a Cu based interconnectionlayer.

The present invention can be also applied to the case using a metalother than a Cu based metal as the interconnection material. In thiscase, the present invention can keep up with the future LSIs by suitablyselecting the material of the adhesion layer for increasing the adhesionbetween electrode pads and a barrier metal film in consideration of thenew interconnection material other than Cu.

Although the adhesion layers 20a and 20b are formed by the sputteringmethod in the above embodiment; however, they may be formed by theelectrolytic plating method or CVD method.

While the preferred embodiments of the present invention have beendescribed using specific terms, such description is for illustrativepurposes only, and it is to be understood that the structure of thesemiconductor device and the processing conditions of the fabricationmethod for the semiconductor device may be suitably changed withoutdeparting from the spirit or scope of the present invention.

What is claimed is:
 1. A semiconductor device comprising: Asemiconductor substrate in contact with a multilayer interconnectionlayer, said multilayer interconnection layer comprising an electrode padportion as an external connection terminal of the multilayerinterconnection layer, said multilayer interconnection layer and saidelectrode pad portion made from copper or an alloy containing copper; anadhesion layer formed directly on the electrode pad portion such thatthe adhesion layer is in contact with the electrode pad portion; abarrier layer formed on the adhesion layer, wherein such barrier layerhas a stacked structure of at least two different types of metal; and asolder bump formed on the barrier layer.
 2. A semiconductor deviceaccording to claim 1, wherein said adhesion layer is made from at leastone kind of metal selected from a group consisting of Al, Cr, Co, Ni,Mo, Ag, Ta, W and Au, or an alloy containing said at least one kind ofmetal.
 3. A semiconductor device comprising: a semiconductor substratein contact with a multilayer interconnection layer, said multilayerinterconnection layer comprising an electrode pad portion as an externalconnection terminal of the multilayer interconnection layer, saidmultilayer interconnection layer and said electrode pad portion madefrom copper or an alloy containing copper; an adhesion layer formeddirectly on the electrode pad portion such that the adhesion layer is incontact with the electrode pad portion; a first passivation layer formedon said adhesion layer; a barrier layer formed on the adhesion layer,wherein such barrier layer has a stacked structure of at least twodifferent types of metal; and a solder bump formed on the barrier layer,wherein said adhesion layer has an upper surface including a firstportion that is in contact with said first passivation layer and asecond portion that contacts a bottom surface of said barrier layer. 4.A semiconductor device according to claim 3 wherein said firstpassivation layer has a lower surface that is in contact with saidadhesion layer, an upper surface that is in contact with said barrierlayer, and a side surface that is in contact with said barrier layer,wherein said side surface extends from said lower surface to said uppersurface.
 5. A semiconductor device according to claim 3, wherein saidadhesion layer comprises Al.
 6. A semiconductor device according toclaim 3, wherein said adhesion layer comprises Co.
 7. A semiconductordevice according to claim 3, wherein said adhesion layer comprises Ni.8. A semiconductor device according to claim 3, wherein said adhesionlayer comprises Ta.
 9. A semiconductor device according to claim 3,wherein said adhesion layer comprises W.
 10. A semiconductor deviceaccording to claim 3, wherein said adhesion layer comprises Au.
 11. Asemiconductor device according to claim 3, further comprising a secondpassivation layer formed between said electrode pad portion and saidfirst passivation layer.
 12. A semiconductor device according to claim11, wherein said second passivation layer has a lower surface that is incontact with said electrode pad portion, an upper surface that is incontact with said first passivation layer, and a side surface that is incontact with said first passivation layer, wherein said side surfaceextends from said lower surface to said upper surface.
 13. Asemiconductor device according to claim 11, wherein said firstpassivation layer is made of polyimide, and said second passivationlayer is made of silicon nitride.
 14. A semiconductor device accordingto claim 3, wherein a thickness of the barrier layer is thicker than athickness of the adhesion layer.
 15. A semiconductor device according toclaim 3, wherein the multilayer interconnection layer and the electrodepad portion are made from the same material.
 16. A semiconductor deviceaccording to claim 3, wherein said adhesion layer substantially contactsan entire bottom surface of said barrier layer.
 17. A semiconductordevice comprising: a semiconductor substrate in contact with amultilayer interconnection layer, said multilayer interconnection layercomprising an electrode pad portion as an external connection terminalof the multilayer interconnection layer, said multilayer interconnectionlayer and said electrode pad portion made from copper or an alloycontaining copper; an adhesion layer formed directly on the electrodepad portion such that the adhesion layer is in contact with saidelectrode pad portion; a first passivation layer formed on said adhesionlayer, a barrier layer formed on said adhesion layer, wherein suchbarrier layer has a stacked structure of at least two different types ofmetal; and a solder bump formed on the barrier layer, wherein said firstpassivation layer has an opening through which said barrier layer iselectrically connected to said adhesion layer.
 18. A semiconductordevice according to claim 17, wherein said first passivation layer isformed directly on said adhesion layer, and said barrier layer is formeddirectly on said adhesion layer.
 19. A semiconductor device according toclaim 17, wherein said adhesion layer comprises Ta.
 20. A semiconductordevice according to claim 17, wherein a thickness of the barrier layeris thicker than a thickness of the adhesion layer.
 21. A semiconductordevice according to claim 17, wherein the multilayer interconnectionlayer and the electrode pad portion are made from the same material. 22.A semiconductor device according to claim 17, wherein said adhesionlayer substantially contacts an entire bottom surface of said barrierlayer.
 23. A semiconductor device according to claim 17, furthercomprising a second passivation layer formed between said electrode padportion and said first passivation layer.
 24. A semiconductor deviceaccording to claim 23, wherein said second passivation layer has a lowersurface that is in contact with said electrode pad portion, an uppersurface that is in contact with said first passivation layer, and a sidesurface that is in contact with said first passivation layer, whereinsaid side surface extends from said lower surface to said upper surface.